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integrated circuit systems, inc. general description features ics9248-72 block diagram frequency timing generator for pentium ii systems 9248-72 rev b 7/28/99 pin configuration 48-pin ssop ? up to 200mhz frequency support. ? power down feature. ? spread spectrum for emi control (0 to ?0.5% down spread , + 0.25% center spread) ?i 2 c interface. ? vddl=2.5v,vdd=3.3v the ics9248-72 is a main clock synthesizer chip for pentium ii based systems using rambus interface drams. this chip provides all the clocks required for such a system when used with a direct rambus clock generator(drcg) chip such as the ics9211-01. spread spectrum may be enabled by driving the spread# pin active. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248- 72 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. the cpu/2 clocks are inputs to the drcg. preliminary product preview * 250k ohm pull-up to vdd on indicated inputs. 1.these pins will have 2x drive strength key specification ? cpu output jitter: <250ps ? cpu/2 output jitter. <250ps ? ioapic output jitter: <500ps ? 48mhz, 3v66, pci output jitter: <500ps ? ref output jitter. <1000ps ? cpu output skew: <175ps ? ioapic output skew <250ps ? pci output skew: <500ps ? 3v66 output skew <250ps ? cpu to 3v66 output offset: 0.0 - 1.5ns (cpu leads) ? 3v66 to pci output offset: 1.5 - 4.0ns (3v66 leads) ? cpu to ioapic output offset 1.5 - 4.0ns (cpu leads) product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.
2 ics9248-72 preliminary product preview pin descriptions pin number pin name type description 1, 45, 46 ioapic[2:0] output 2.5v ioapic clock outputs 2 ref0 output 3.3v, 14.318 mhz reference clock output. 3, 24, 29, 33 vdd power 3.3 v power 4 x1 input 14.318 mhz crystal input 5 x2 output 14.318 mhz crystal output 6, 14, 20, 26, 32 gnd power ground fs [2:1] in frequency select pins. latched inputs determins the cpu & pci frequencies. pciclk [1:0] output 3.3 v pci clock outputs, generating timing requirements for 9,17 vddpci power 3.3 v power for the pci clock outputs 19, 18, 16, 15, 13, 12, 11, 10 pciclk [9:2] output 3.3 v pci clock outputs 23, 22, 21 3v66 output 3.3 v 66 mhz clock output, fixed frequency clock typically used with agp 25 sel 133/100# input control for the frequency of clocks at the cpu output pins. if logic "0" is used the 100 mhz frequency is selected. if logic "1" is used, the 133 mhz frequency is selected. the pci clock is multiplexed to run at 33.3 mhz for both selected cases. fs0 in frequency select pin. latched inputs determins the cpu & pci frequencies. 48 mhz output 3.3 v 48 mhz clock output, fixed frequency clock typically used with usb devices sel24/48 in 48/24 mhz select option. active low = 48 mhz output. active high = 24 mhz 24_48mhz# output 3.3v 48 or 24 mhz clock output, fixed frequency clock typically used with usb devices. 30 sclk in clock input of i2c input 31 pd# input asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. 34 sdata in data input for i 2 c serial input. 36, 35 cpuclk [1:0] 0utput 2.5 v cpu and host clock outputs 37, 40 vddlcpu power 2.5 v power for the cpu and host clock outputs 41 gndlcpu/2 power ground for the cpu and host clock outputs 42 cpu/2 output output running at 1/2 cpu clock frequency.synchronous to the cpu outputs. 43 vddlcpu/2 power 2.5 v power for the cpu/2 clock outputs 47 gndlioapic power ground for ioapic clocks 48 gndref power ground for 14.318 mhz reference clock outputs 8, 7 28 27 power groups: vddref, gndref = ref, x1, x2 gndpci, vddpci = pciclk vdd66, gnd66 = 3v66 vdd48, gnd48 = 48mhz vddcor, gndcor = pll core vddlcpu/2 , gndlcpu/2 = cpu/2 vddlioapic, gndioapic = ioapic
3 ics9248-72 preliminary product preview ics9248-72 power management features: note: 1. low means outputs held static low as per latency requirement next page. 2. on means active. 3. pd# pulled low, impacts all outputs including ref and 48 mhz outputs. # d pk l c u p c2 / u p cc i p a o i6 6 v 3i c pf _ i c p . f e r z h m 8 4 c s os o c v 0w o lw o lw o lw o lw o lw o lw o lf f of f o 1n on on on on on on on on o power management requirements: note: 1. clock on/off latency is defined in the number of rising edges of free running pciclks between the clock disable goes low/ high to the first valid clock comes out of the device. 2. power up latency is when pwr_dwn# goes inactive (high to when the first valid clocks are dirven from the device. l a g n i se t a t s l a g n i s y c n e t a l s e g d e g n i s i r f o . o n k l c i c p f o # d p ) n o i t a r e p o l a m r o n ( 1s m 3 ) n w o d r e w o p ( 0. x a m 2 functionality v dd = 3.3v5%, v ddl = 2.5v 5% ta= 0 to 70c crystal (x1, x2) = 14.31818mhz sel133/100# fs2 (mhz) fs1 (mhz) fs0 (mhz) cpu (mhz) cpu/2 (mhz) pci (mhz) 3v66 (mhz) ioapic (mhz) 1111 133.30 66.65 33.325 66.65 16.66 1 1 10 138.01 69.01 34.505 69.01 17.25 1 1 01 142.91 71.45 35.725 71.45 17.86 1 10 0 147.95 73.98 36.99 73.98 18.49 1011 152.49 76.24 38.12 76.24 19.06 1010 156.99 78.49 39.245 78.49 19.62 1001 162.02 81.01 40.505 81.01 20.25 1000 180.00 89.99 30.00 60.00 15.00 0111 100.23 50.11 33.405 66.81 16.70 0110 105.00 52.49 35 70.00 17.50 0101 113.99 56.99 37.83 75.66 18.91 0100 120.00 59.99 40.00 80.00 20.00 0011 128.51 64.25 32.125 64.25 16.06 0010 200.01 100.00 33.33 66.66 16.66 0001 170.03 85.01 28.33 56.66 14.16 0000 66.82 33.40 33.40 66.80 16.7
4 ics9248-72 preliminary product preview 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte coun t ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ac k byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ac k stop bit how to write:
5 ics9248-72 preliminary product preview byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note1: default at power-up will be for latched logic inputs to define frequency. t i bn o i t p i r c s e dd w p t i b ) 4 : 7 ( t i b k l c u p c2 / u p c6 6 v 3k l c i c pc i p a o i0 7654 1111 0 3 . 3 3 15 6 . 6 65 6 . 6 65 2 3 . 3 36 6 . 6 1 x x x x 1 e t o n 1110 1 0 . 8 3 11 0 . 9 61 0 . 9 65 0 5 . 4 35 2 . 7 1 1101 1 9 . 2 4 15 4 . 1 75 4 . 1 75 2 7 . 5 36 8 . 7 1 1100 5 9 . 7 4 18 9 . 3 78 9 . 3 79 9 . 6 39 4 . 8 1 1011 9 4 . 2 5 14 2 . 6 74 2 . 6 72 1 . 8 36 0 . 9 1 1010 9 9 . 6 5 19 4 . 8 79 4 . 8 75 4 2 . 9 32 6 . 9 1 1001 2 0 . 2 6 11 0 . 1 81 0 . 1 85 0 5 . 0 45 2 . 0 2 1000 0 0 . 0 8 19 9 . 9 80 0 . 0 60 0 . 0 30 0 . 5 1 0111 3 2 . 0 0 11 1 . 0 51 8 . 6 65 0 4 . 3 30 7 . 6 1 0110 0 0 . 5 0 19 4 . 2 50 0 . 0 75 30 5 . 7 1 0101 9 9 . 3 1 19 9 . 6 56 6 . 5 73 8 . 7 31 9 . 8 1 0100 0 0 . 0 2 19 9 . 9 50 0 . 0 80 0 . 0 40 0 . 0 2 0011 1 5 . 8 2 15 2 . 4 65 2 . 4 65 2 1 . 2 36 0 . 6 1 0010 1 0 . 0 0 20 0 . 0 0 16 6 . 6 63 3 . 3 36 6 . 6 1 0001 3 0 . 0 7 11 0 . 5 86 6 . 6 53 3 . 8 26 1 . 4 1 0000 2 8 . 6 60 4 . 3 30 8 . 6 60 4 . 3 37 . 6 1 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 2 t i b % 5 2 . 0 e p y t d a e r p s r e t n e c m u r t c e p s d a e r p s - 0 % 5 . 0 - o t 0 e p y t d a e r p s n w o d m u r t c e p s d a e r p s - 1 1 1 t i b l a m r o n - 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r = 0 s t u p t u o l l a e t a t s i r t = 1 0
6 ics9248-72 preliminary product preview byte 1: cpu, cpu/2, 48mhz register (1 = enable, 0 = disable) byte 2: pciclk active/inactive register (1 = enable, 0 = disable) byte 3: 3v66, ref register active/inactive (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b7 21 z h m 8 4 6 t i b8 21 z h m 8 4 _ 4 2 5 t i b-- ) d e v r e s e r ( 4 t i b2 412 / u p c 3 t i b-- ) d e v r e s e r ( 2 t i b9 31 2 k l c u p c 1 t i b6 31 1 k l c u p c 0 t i b5 31 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b6 11 7 k l c i c p 6 t i b5 11 6 k l c i c p 5 t i b3 11 5 k l c i c p 4 t i b2 11 4 k l c i c p 3 t i b1 11 3 k l c i c p 2 t i b0 11 2 k l c i c p 1 t i b81 1 k l c i c p 0 t i b71 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) d e v r e s e r ( 6 t i b3 21 2 _ 6 6 v 3 5 t i b2 21 1 _ 6 6 v 3 4 t i b1 21 0 _ 6 6 v 3 3 t i b-x# 2 s f 2 t i b-x # ) # 8 4 4 2 l e s ( 1 t i b9 11 9 k l c i c p 0 t i b8 11 8 k l c i c p byte 5: cpu, ioapic register active/inactive (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) d e v r e s e r ( 6 t i b-0 ) d e v r e s e r ( 5 t i b-0 ) d e v r e s e r ( 4 t i b-0 ) d e v r e s e r ( 3 t i b-0 ) d e v r e s e r ( 2 t i b-0 ) d e v r e s e r ( 1 t i b-0 ) d e v r e s e r ( 0 t i b-0 ) d e v r e s e r ( byte 4: ioapic, ref register active/inactive (1 = enable, 0 = disable) notes: 1. inactive means outputs are held low and are disabled from switching. t i b# n i pd w pn o i t p i r c s e d 7 t i b0) d e v r e s e r ( 6 t i b11 2 c i p a o i 5 t i b5 41 1 c i p a o i 4 t i b6 41 0 c i p a o i 3 t i b-0 ) d e v r e s e r ( 2 t i b-x# 0 s f 1 t i b-x# 1 s f 0 t i b21 ) 2 x ( f e r
7 ics9248-72 preliminary product preview pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. pci_stop# and cpu_stop# are considered to be don't cares during the power down operations. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz.
8 ics9248-72 preliminary product preview absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5%, vddl=2.5 v+ 5%(unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors m a input low current i il2 v in = 0 v; inputs with pull-up resistors m a operating i dd3.3op c l = 0 pf; select ma supply current power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd m a supply current input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance l pin 7nh input capacitance 1 c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guarenteed by design, not 100% tested in production. delay group offset group offset measurement loads measure points cpu to 3v66 0.0-1.5ns cpu leads cpu @ 20pf, 3v66 @ 30pf cpu @1.25v, 3v66 @ 1.5v 3v66 to pci 1.5-4.0ns 3v66 leads 3v66 @ 30pf, pci @ 30pf 3v66 @ 1.5v, pci @ 1.5v cpu to ioapic 1.5-4.0ns cpu leads cpu @ 20pf, ioapic @ 20pf cpu @1.25v, ioapic @ 1.5v note: 1. all offsets are to be measured at rising edges.
9 ics9248-72 preliminary product preview electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 w output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 55 ns skew t sk2b 1 v t = 1.25 v 175 ps jitter t j c y c-c y c 1 v t = 1.25 v 250 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu/2 t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 w output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 55 ns jitter t j c y c-c y c 1 v t = 1.25 v 250 ps 1 guarenteed by design, not 100% tested in production.
10 ics9248-72 preliminary product preview electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -29 -23 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 500 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 w output impedance r dsn1 1 v o = v dd *(0.5) 12 55 w output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2.0 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2.0 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 250 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production.
11 ics9248-72 preliminary product preview electrical characteristics - ioapic t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 40 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 w output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 45 55 ns skew t sk2b 1 v t = 1.25 v 250 ps jitter t jcyc-cyc 1 v t = 1.25 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - 48m, ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 w output impedance r dsn5 1 v o = v dd *(0.5) 20 60 w output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v output high current i oh5 v oh @min =1 v, v oh@max = 3.135 v -29 -23 ma output low current i ol5 v ol@min =1.95 v, v ol@min =0.4 v 29 27 ma duty cycle d t5 1 v t = 1.5 v 45 55 % jitter t jcyc-cyc 1 v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc 1 v t = 1.5 v; ref clocks 1000 ps skew t sk v t = 1.5 v,fixed clocks n/a ps 1 guarenteed by design, not 100% tested in production.
12 ics9248-72 preliminary product preview 48 pin ssop package l o b m y s s n o i s n e m i d n o m m o c s n o i t a i r a v d n . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .1 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a8 8 0 .0 9 0 .2 9 0 . b8 0 0 .0 1 0 .5 3 1 0 . c5 0 0 .- 0 1 0 . ds n o i t a i r a v e e s e2 9 2 .6 9 2 .9 9 2 . ec s b 5 2 0 . 0 h0 0 4 .6 0 4 .0 1 4 . h0 1 0 .3 1 0 .6 1 0 . l4 2 0 .2 3 0 .0 4 0 . ns n o i t a i r a v e e s 0 5 8 x5 8 0 .3 9 0 .0 0 1 . ordering information ics9248 y f-72 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice.

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